This invention relates generally to data processing systems, and, more particularly, to the detection of processing errors or malfunctions in duplicated logic units.
One of the most comprehensive schemes for detecting processing errors or malfunctions in data processing systems involves duplicating the data processing control units, running the two units in parallel with the same inputs, and comparing the two outputs for identity with bit-by-bit matching circuitry. If the data thus obtained does not match, either different input data was received by the units or one of the units is not operating properly.
In a processing arrangement employing duplicated processing units, it is imperative that processing errors or malfunctions in either processing unit are detected immediately upon their occurrence. Immediate error detection facilitates timely diagnosis of processing errors or malfunctions and permits appropriate action to be taken before spurious system control operations occur. Bit-by-bit matching provides a complete and accurate method of detection, but is slow to react due to the extensive matching circuitry required.
Today, many data processing systems utilize positive-voltage, transistor-transistor logic. With a positive source voltage of approximately 5.0 volts, a high voltage (binary "1") is a positive voltage of approximately 3.6 volts; while a low voltage (binary "0") is as near to zero volts as the saturation voltage of the collector-to-emitter structure of a transistor will allow, typically +0.2 volts. No matter what kind of electronic circuits are used to build data processing systems, the basic digital building blocks are very similar from system to system. In transistor-transistor logic, the NAND gate is the basic building block. With the basic gate, counters, flipflops, shift-registers, and other circuits can be built. These, in turn, are used to build the desired data processing system. The basic NAND gate comprises an input stage and an output stage, the latter being arranged to provide a source of and a sink for current for a given load. These characteristics, when utilized with appropriately connected, duplicated logic units, according to the principles of this invention, allows a current imbalance to be detected between mismatched units.
It is an objective of this invention to provide an immediate detection of a mismatch caused by processing errors or malfunctions between duplicated logic units while utilizing the output stage of the NAND gate. Where the data processing system uses transistor-transistor logic, the detection circuit of this invention can economically take advantage of the characteristic of the output stage of the already present gates.